The present invention relates to the field of voltage converters. More particularly, the present invention relates to prevention of over-current conditions in voltage converters.
In a conventional voltage converter, an output voltage is typically monitored, compared to a predetermined desired level and a response is developed to more precisely attain the desired output voltage. More particularly, to adjust the output voltage, the input current is modulated up or down. Conventional modulation techniques include pulse-width modulation (PWM) and frequency modulation.
FIG. 1 illustrates a voltage converter of the prior art. An unregulated direct-current DC voltage source Vin1 is coupled to a first terminal of a switch SW1. A second terminal of the switch SW1 is coupled to a first terminal of an inductor L1 and to a first terminal of a switch SW2. A second terminal of the inductor L1 is coupled to a first terminal of an output capacitor C1. A second terminal of the switch SW2 and a second terminal of the capacitor C1 are coupled to ground.
When the switch SW1 is closed, the switch SW2 is open. Under these conditions, current flows from the input source Vin1 through the inductor L1 and charges the capacitor C1. Thus, an output voltage Vout1 formed across the capacitor C1 tends to increase. When the switch SW1 is open, the switch SW2 is closed. Under these conditions, current from the capacitor C1 flows through the inductor L1 and to ground. Thus, the output voltage Vout1 tends to decrease. A load 10 coupled across the capacitor C1 is powered by the voltage converter.
A first terminal of a resistor R1 is coupled to the first terminal of the capacitor C1. A second terminal of the resistor R1 is coupled to a first terminal of a resistor R2. A second terminal of the resistor R2 is second terminal of the capacitor C1.
The resistors R1 and R2 form a voltage divider, in which a voltage formed at an intermediate node is proportional to the output voltage Vout1. This voltage is coupled to an inverting input of an amplifier 12. A reference voltage Vref1 is coupled to a non-inverting input of the amplifier 12. The amplifier 12 forms an error signal Veao1 that is representative of a difference between the output voltage Vout1 and a desired level for the output voltage Vout1.
The error signal Veao1 is coupled to a non-inverting input of a comparator 14. A periodic ramp signal Vramp1 formed by an oscillator 16 is coupled to an inverting input of the comparator 14. The comparator 14 forms a switch control signal Vsw1 that is coupled to the switch SW1 and to an input of an inverter 18. An output of the inverter 18 is coupled to the switch SW2.
As can be seen from FIG. 1, when the error signal Veao1 is higher than the ramp signal Vramp1, the switch control signal Vsw1 is a logic high voltage. Under these conditions, the switch SW1 is closed and the switch SW2 is open. When the error signal Veao1 is lower than the ramp signal Vramp1, the switch control signal Vsw1 is a logic low voltage. Under these conditions, the switch SW1 is open and the switch SW2 is closed.
The ramp signal Vramp1 rises steadily to a maximum level and then rapidly discharges to a minimum level before the cycle repeats. The error signal Veao1 generally remains between maximum and minimum levels of the ramp signal Vramp1. Thus, for each cycle of the ramp signal Vramp1, the switches SW1 and SW2 cycle between opened and closed.
When the output voltage Vout1 decreases, the error signal Veao1 increases. This increases the duty cycle for the switch SW1 and, thus, increases the output voltage Vout1. When the output voltage Vout1 increases, the error signal Veao1 decreases. This decreases the duty cycle for the switch SW1 and, thus, decreases the output voltage Vout1. Accordingly, the output voltage Vout1 is regulated in a feedback loop.
If the output voltage Vout1 is significantly below the desired level, then the switch SW1 may be closed for a significant portion of the time. As a result, the input current can be of a large magnitude. Further, if the input voltage Vin1 should rise unexpectedly, this can also contribute to a large input current. A large input current may cause damage to elements of the converter, such as the switch SW1. Accordingly, it may be desirable to provide a technique for limiting the input current to the converter.
Therefore, what is needed is a technique for limiting the input current to a voltage converter. It is to these ends that the present invention is directed.
The invention is a current limiting technique for a voltage converter. The level of input current to the converter is determined. If the measured current level is excessive, then switching in the converter may be interrupted or the duty cycle reduced until the current falls to an acceptable level. Because parasitic resistance may be used to detect the input current, rather than a dedicated sensing resistor, fewer components may be required. Thus, implementation of the converter and its associated control circuitry is simplified.
In accordance with one aspect of the invention, a current through a reactive element in a voltage converter is limited. Current from a supply is switched through a reactive element in accordance with a switch control signal for forming a regulated output voltage in a feedback loop. A first signal that is representative of the input current is sensed. A voltage that is representative of the output voltage of the voltage converter is sensed. A second signal that is representative of a difference between the output voltage and a desired voltage is formed. A selected one of the first signal and the second signal is compared to a ramp signal for forming the switch control signal wherein the selected one of the first signal and the second signal is selected according to the relative magnitudes of the first and second signal.